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Because the TLB is essentially a cache, putting all of these concepts together can
be confusing. A walkthrough of the entire process will help you to grasp the overall
idea. When the CPU generates an address, it is an address relative to the program
itself, or a virtual address. This virtual address must be converted into a
physical address before the data retrieval can proceed. There are two ways this is
accomplished: (1) use the TLB to find the frame by locating a recently cached
(page, frame) pair; or (2) in the event of a TLB miss, use the page table to find the
corresponding frame in main memory (typically the TLB is updated at this point
as well). This frame number is then combined with the offset given in the virtual
address to create the physical address.
At this point, the virtual address has been converted into a physical address
but the data at that address has not yet been retrieved. There are two possibilities
for retrieving the data: (1) search cache to see if the data resides there; or (2) on a
cache miss, go to the actual main memory location to retrieve the data (typically
cache is updated at this point as well).
Figure 6.18 illustrates the process of using a TLB, paging, and cache memory.
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