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From a programmer’s point of view, the interface hardware is invisible. Instead,
the programmer thinks of the bus as defining an address space. From an architect’s
point of view, the address space must be created from independent memories.
The key to creating a single address space lies in memory configuration — each
memory is configured to respond to a specific set of addresses. That is, the interface for
memory 1 is assigned a different set of addresses than the interface for memories 2, 3,
4, and so on. When a processor places a fetch or store request on the bus, all memory
controllers receive the request. However, only one memory responds. That is, each
memory interface compares the address in the request to the set of addresses for which
the memory has been configured. If the address in the request lies within the
controller’s set, the controller responds. The point is:
Although an interface receives all requests that pass across the bus,
the interface only responds to requests that contain an address for
which the interface has been configured.
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