Although the bus operations are named fetch and store, a device interface is not a
memory — data is not stored for later recall. That is, from the perspective of a device,
the address in a request merely consists of a set of bits. The interface contains logic circuits
that compare the address bits in each request to the addresses assigned to the device.
If a match occurs, the interface enables a circuit that handles the operation (fetch
or store). For example, the first item in Figure 14.10 can be implemented by hardware
that tests the address, operation, and data items in each request. We think of the test as
a conditional operation: