We said that because a parallel interface supports simultaneous transfer, a memory
interface with many wires has higher performance than a memory interface with fewer
wires. Because a byte is smaller than a typical word, a memory system that offers byte
addressing will have lower performance than a memory system that offers word addressing.
Can we devise a memory system that combines the higher speed of word addressing
with the programming convenience of byte addressing? Yes. To do so, we need an
intelligent memory controller that can translate between the two addressing schemes.
The controller accepts byte addresses from the processor, and uses word addresses for
the underlying memory — when the processor requests a byte, the controller reads the
appropriate word of memory and extracts the specified byte. Figure 10.7 illustrates a
mapping between the two addressing schemes.