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The refresh hardware is more complex than the figure implies. To keep the refresh
circuit small, architects do not build one refresh circuit for each bit. Instead, a single,
small refresh mechanism is designed that can cycle through the entire memory. As it
reaches a bit, the refresh circuit reads the bit, writes the value back, and then moves on.
Complexity also arises because a refresh circuit must coordinate with normal
memory operations. In addition to avoiding delay, the hardware must ensure that the
value of a bit does not change between the time the refresh circuit reads the bit and the
time the refresh circuit writes the same value back. Despite the need for a refresh circuit,
the cost and power consumption advantages of DRAM are so great that most computer
memory is composed of DRAM rather than SRAM.
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