Performing a division or computing a remainder is time consuming and requires
extra hardware (e.g., an Arithmetic Logic Unit). To avoid computation, architects organize
memory using powers of two. Doing so means that hardware can perform the
two computations above simply by extracting bits. In Figure 10.7, for example, N=22,
which means that the offset can be computed by extracting the two low-order bits, and
the word address can be computed by extracting everything except the two low-order
bits. Figure 10.8 illustrates the idea: