Most PCs are held back not by the s

Most PCs are held back not by the speed of their main processor, but by the time it takes to move data in and out of memory. One of the most important techniques for getting around this bottleneck is the memory cache.
The idea is to use a small number of very fast memory chips as a buffer or cache between main memory and the processor. Whenever the processor needs to read data it looks in this cache area first. If it finds the data in the cache then this counts as a 'cache hit' and the processor need not go through the more laborious process of reading data from the main memory. Only if the data is not in the cache does it need to access main memory, but in the process it copies whatever it finds into the cache so that it is there ready for the next time it is needed. The whole process is controlled by a group of logic circuits called the cache controller.
One of the cache controller's main jobs is to look after 'cache coherency' which means ensuring that any changes written to main memory are reflected within the cache and vice versa. There are several techniques for achieving this, the most obvious being for the processor to write directly to both the cache and main memory at the same time. This is known as a 'write-through' cache and is the safest solution, but also the slowest.
The main alternative is the 'write-back' cache which allows the processor to write changes only to the cache and not to main memory. Cache entries that have changed are flagged as 'dirty' telling the cache controller to write their contents back to main memory before using the space to cache new data. A write-back cache speeds up the write process, but does require a more intelligent cache controller.
Most cache controllers move a 'line' of data rather than just a single item each time they need to transfer data between main memory and the cache. This tends to improve the chance of a cache hit as most programs spend their time stepping through instructions stored sequentially in memory, rather than jumping about from one area to another. The amount of data transferred each time is known as the 'line size'.

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大多数的个人电脑都没有按他们的主处理器的速度进行，但是通过移动数据在内存中的时间。其中一个最重要的技术就是要把这个瓶颈问题是内存缓存，而这个想法是用少量的非常快的内存芯片作为主内存和处理器之间的缓冲区或高速缓存。每当处理器需要读取数据时，它先在这个高速缓存区中读取数据。如果在缓存中找到了数据，那么这个数据就被当作一个“缓存命中”，而处理器不需要通过主内存的读取数据的更费力的过程。如果数据不在缓存中，它就需要访问主内存，但在这个过程中，它会复制到缓存中的任何一个，所以它是有准备的下一次，它是必要的。整个过程是由一组逻辑电路控制，称为高速缓存控制器。
一体的高速缓存控制器的主要工作是照顾的缓存一致性”意味着确保写入内存的任何变化都反映在缓存，反之亦然。实现这一点的技术有几个，最明显的是处理器直接写入缓存和主内存的同时。这是众所周知的“写通过”缓存，是最安全的解决方案，但也是最慢的，主要的替代是“写回”高速缓存，这使得处理器写的变化，只有到高速缓存，而不是主内存。高速缓存条目已更改标记为“脏”告诉缓存控制器写回主存的内容之前，利用空间来缓存新的数据。一个写回高速缓存的写入过程，但需要一个更智能的高速缓存控制器。大多数高速缓存控制器移动一个“行”的数据，而不是一个单一的项目，每一次，他们需要在主内存和高速缓存之间的数据传输。这有可能提高高速缓存命中的机会，因为大多数的程序花费他们的时间步进通过指令存储在内存中，而不是从一个区域跳到另一个。每次传输的数据量被称为“线大小”。